A Virtual Layer for FPGA Based Parallel Systems (MP-SoCs)

Besides performance and time to market, robustness and reliability are important design targets for modern Systemson-Chip (SoCs). Despite these features the power consumption must be as low as possible. To meet these design goals parallel, flexible, and adaptive architectures are required [1]. Today, dynamically reconfigurable FPGAs are well suited to form a parallel architecture because they incorporate serveral hardand softcores. To efficiently use such multicore systems a hardware independent system must be created which handles all cores. Further, optimizing the power management the number of active cores must be adapted dynamically to the current workload. To make these features manageable and augment the system with adaptivity a virtual layer is required which hides the – due to runtime reconfiguration – changing hardware system from the application software. The Scalable Dataflow-driven Virtual Machine [2] is such a virtualization of a parallel, adaptive and heterogeneous cluster of processing elements (PE). Thus, it is well suited to serve as a managing firmware for multicore FPGAs.